Ceramics have found widespread use in electronics as a substrate for integrated circuit packages. Metallized circuit patterns are applied to the ceramic substrate, and ceramic and metallization are co-sintered to create a monolith of substrate and circuitry. Multi-layer circuit packages are constructed by combining ceramic particles and organic binder unto unfired, or "green," tape. Inter-layer conductive paths, known as "vias," are then inserted through the layers, forming electrical interconnections between the circuits on each layer after they are stacked and processed. Thereafter, metallized circuit patterns are applied. The tape layers typically have thicknesses ranging from 5 to 25 mils. Holes and notches are formed in the layers as required. Multiple layers of printed tape are stacked and then laminated under pressure, and ceramic and metallization co-sintered to form a monolithic structure with three-dimensional circuitry.
Typically, substrates are formed from a combination of approximately 90-94% commercial alumina, and 6-10% silicon-based glass, and tungsten or molybdenum/manganese paste is used to form the metallized conductive paths. The glass is added to the alumina to promote bonding of the tungsten to the alumina and to provide sintering of the alumina at a lower temperature than for 98+% commercial alumina. In prior art 100% tungsten paste formulations, the glass component is used in the alumina substrate to facilitate adhesion of the tungsten and alumina particles. Upon firing, the glass component migrates into the tungsten layer, providing interface adhesion between the paste component and substrate. Circuit packages produced from this prior art formulation display a dielectric constant of approximately 9-9.5, thermal conductivity of approximately 0.045(cal cm/cm.sup.2 sec C..degree.) at 20.degree. C. (compared with 0.85(cal cm/cm.sup.2 sec C..degree.) for 99.5% aluminal), shrinkage variability of 0.5% -1.0%, and a surface finish of greater than 25 microinches. While these substrate properties may have been acceptable for conventional semiconductor packages, they are inadequate for high-performance large scale integration circuitry.
Surface finish becomes increasingly important as the size of circuit features such as pads and vias decreases. In microelectronic circuits produced by thin-film metallization techniques, the conductor thickness can be as small as a few microns (1 micron=40 microinches), so that if the substrate has a 25 microinches surface finish typical of the prior art, the conductor path will have substantial differences in thickness along its length, or may even be discontinuous, with a corresponding deterioration in function. Accordingly, roughness of surface finish prevents post-firing circuit personalization by thin-film metallization.
Moreover, porosity of the as-fired surface, especially when combined with roughness of the surface, leads to the problem of retention of plating salts. Aggressive cleaning procedures are required to avoid deposition of plating where not desired, and to avoid blistering upon firing. Greater smoothness and lack of porosity would allow the use of more active catalysts, which, in turn would increase product yield through electroless plating operations.
Reduction in shrinkage variability is also especially important as feature size decreases, and a reduction in shrinkage variability from the prior art 0.5-1% level would increase yield. This is because variability in shrinkage prevents precise location of integrated circuit pads, vias, and other device interconnects and increases the probability of discontinuities necessitating discarding of the product. The need for reduction in shrinkage variability extends to both the manufacturer of substrates and the substrate consumer, who requires precise positioning of devices and interconnects and, in a few special cases, reliable circuit personalization by thin-film metallization.
Accodingly, there exists a need for a substrate/metallization system with greater thermal conductivity, lower shrinkage variability, and better surface finish, while maintaining the desired dielectric and electrical properties.